One technical area in which components are produced from a body is semiconductor technology, where semiconductor wafers are separated into individual electronic devices.
Such a process for separating a wafer into chips is disclosed in DE 43 17 721. The wafer has an SOI (silicon-on-insulator) layer. Between the chips, moats are etched down to the insulator layer. Then, spacers are formed for passivating silicon-oxide layers of the chips, and finally, the chips are separated by etching away the insulator layer.
German Patent Application No. 195 38 634.5, which was not published prior to the filing date of the present application, discloses another process for separating a semiconductor wafer into electronic devices. In this process, the electronic devices are separated by removing material in separation regions of the semiconductor wafer. In a wafer area to be thinned, a retardation layer is provided which retards the removal of material and has openings in the separation regions. With this process, even very thin electronic devices can be readily separated from a relatively thick semiconductor wafer as is commonly used for stability reasons. The thickness of the semiconductor wafer is reduced simultaneously with the separation process. The devices are separated simultaneously by removing the material in the separation regions of the semiconductor wafer. The material of the retardation layer is chosen to slow down the removal of the material, so that the thickness of the body is reduced more slowly than the device separation takes place.
From Schade, Halbleitertechnologie Band 2, Verlag Technik, Berlin 1983, page 21 et seq., it is known to form patterns of migration-capable material in a semiconductor. A migration-capable material, such as aluminum, is deposited on the semiconductor by thin-film techniques. By a migration process in which a given temperature gradient is applied to the semiconductor wafer, the material is caused to migrate from the film along the temperature gradient into the semiconductor. With this process, both abrupt pn junctions and enriched regions as well as interconnections through the semiconductor can be formed.
For various applications, it may be desirable to produce spatially patterned components. In semiconductor technology, such components can be used as heatsinks, for example. They can be fabricated separately and be attached to electronic devices. However, it is complicated and costly to produce suitably patterned components, such as microheatsinks, and connect them with electronic devices.
It is also known in practice to produce electronic devices with a cooling system by patterning the backside of the wafer by forming saw lines therein so as to enlarge the wafer back surface. This process has the disadvantage that because of the sawing, the wafer becomes mechanically unstable, and that as a result of the patterning, the wafer may become warped.
Accordingly, it is greatly desired to obtain a simple process for producing spatially patterned components without the above-mentioned disadvantages.